Alibaba Unveils Zhenwu V900 AI Chip with 216 GB

T-Head’s new processor targets 10-trillion-parameter models, but conceals crucial memory speed and fabrication details.

T-Head, the semiconductor division of Alibaba Group, announced the Zhenwu V900, a new artificial intelligence accelerator built for large-scale training and inference in enterprise datacenters. Alibaba chief executive Eddie Wu introduced the chip on September 22, 2026, during the annual Apsara Conference in Hangzhou. According to the company, mass production is scheduled to begin in the first quarter of 2027. Wu described the accelerator as the most capable domestic AI processor designed in China, though the presentation provided no head-to-head benchmark comparisons against rival domestic hardware such as Huawei’s Ascend family.

The announcement highlights Chinese technology companies pushing to build internal hardware stacks amid persistent Western export controls on advanced computing systems. But alongside ambitious performance projections, the briefing left fundamental technical questions unanswered.

Inside the Zhenwu V900: memory and scale

The accelerator integrates 216 GB of memory and delivers 1,200 GB/s of bidirectional chip-to-chip interconnect bandwidth. This interconnect acts as a high-speed pipeline for processors to exchange data directly during distributed workloads without stalling on standard server network links. To run massive neural networks within practical power limits, the silicon includes native hardware support for FP8 and FP4 numerical formats. Computing at lower precision uses fewer bits per operation, reducing memory footprint and electrical demand while preserving model output quality.

Alibaba claims the V900 provides three times the compute throughput of its Zhenwu M890 predecessor, which arrived in May 2026. That multiplier should be treated as an unverified corporate statement. The company released no standardized benchmark suites or third-party validation reports to back up the comparison.

Datacenter supernodes built for Qwen models

Beyond the standalone silicon, T-Head outlined a comprehensive datacenter architecture. The design integrates the accelerator with proprietary ICN network switches, Panmai SmartNICs (specialized adapters that take over network tasks to free up host processors), and Zhenyue solid-state storage controllers. In theoretical terms, Alibaba claims this interconnect mesh can scale up to 500,000 accelerators in a single cluster. To date, no computing facility of that scale has been deployed or publicly demonstrated.

The immediate customer for this computing power is internal. Alibaba plans to use the infrastructure to train future generations of its open Qwen models, targeting between 5 and 10 trillion parameters. On the commercial side, the company states that its Zhenwu processor family currently runs workloads for more than 650 enterprise customers in autonomous driving, energy, and financial services.

Critical omissions on memory and fabrication

Despite the prominent stage presentation, several core engineering metrics were omitted. The advertised 1,200 GB/s throughput applies strictly to external links connecting separate chips. Local on-package memory bandwidth (HBM), the critical data pipeline feeding processor cores that often decides real-world AI training performance, was never disclosed. Any circulating claims regarding the transfer rate of this local memory remain strictly RUMOR.

Alibaba also refused to identify the fabrication foundry or state the manufacturing process node in nanometers. With strict United States trade restrictions blocking advanced lithography equipment from entering China, delivering production volumes by early 2027 remains an open question. T-Head proved its architectural intent, but the real test will only occur when production chips land on server racks and undergo independent scrutiny.