HBM4 on Nvidia Rubin takes 16% of die, SemiAnalysis says

A physical crunch at the silicon edge pushes Nvidia toward custom memory interfaces for its next-generation Feynman processors.

Roughly 16% of the primary compute die on Nvidia’s upcoming Rubin artificial intelligence processor is dedicated purely to memory communication. That technical estimate comes from silicon modeling by independent research firm SemiAnalysis. That footprint of HBM4 on Nvidia Rubin performs no tensor math and holds no model weights. Its only job is routing electrical signals back and forth between compute cores and external high-bandwidth memory (HBM4) stacks.

In semiconductor manufacturing, the raw silicon slice containing the logic circuitry is called a die. On TSMC’s 3-nanometer class nodes, every square millimeter represents expensive manufacturing capacity that designers prefer to fill with compute engines, local cache, and internal interconnects. Giving up nearly a fifth of that surface area to memory traffic imposes a hard physical limit. Because Nvidia does not release micrometer-level floor plans of its silicon, this figure from the firm, which sells commercial advisory services in the chip sector, serves as an engineering model rather than an official manufacturer measurement.

Why HBM4 on Nvidia Rubin consumes so much space

To keep processors fed with data, two structures manage memory traffic: the controller and the physical layer, commonly referred to as the PHY. The controller schedules reads and writes like a digital traffic dispatcher. The PHY sits along the outer boundary of the processor, housing analog and digital circuitry that drives electrical pulses across physical wiring.

The bottleneck stems from the industry’s open standards roadmap. The previous HBM3E generation used 1,024 communication paths per memory stack. To push data rates higher in HBM4, the JEDEC standards group doubled that interface to 2,048 pins, as noted by industry tracking from Chiplog. To link eight HBM4 stacks simultaneously, Nvidia had to line up massive banks of controllers and PHY circuitry around the chip boundary, creating dense wiring congestion at the silicon perimeter.

The pivot to custom memory

To escape this physical crunch, chipmakers are exploring designs beyond standard JEDEC specifications. Technical presentations by Samsung and Marvell at the ECTC 2026 conference showed that replacing standard interfaces with direct die-to-die interconnects cuts memory footprint on the host processor by about 60%. In Samsung’s benchmark, the required interface area fell from 32 square millimeters down to 12.75 square millimeters.

Nvidia’s architectural fix is slated for its next processor family, code-named Feynman. According to SemiAnalysis, Nvidia plans to deploy proprietary custom memory (NVHBM) tied together by a proprietary die-to-die interconnect called NV-HBI. The design moves the memory controller off the expensive GPU compute die and embeds it directly onto the base die of the memory stack. Because HBM4 base dies are moving from legacy DRAM processes to advanced TSMC or Samsung logic nodes, the memory base can run digital control logic on its own.

Nvidia’s targets and the manufacturing risks

If this architectural redesign succeeds on Feynman, SemiAnalysis projects that memory interface circuits will drop from roughly 16% of GPU die area down to about 4%. Nvidia claims the change will free up to 25% more usable die area for compute cores, add up to 30% higher memory bandwidth, and cut memory power consumption by 15% compared to standard HBM4E.

Those performance numbers remain vendor-stated goals that still lack validation in commercial data center deployments. Moving to a proprietary path also carries engineering trade-offs. Leaving JEDEC standards fragments the supply chain and increases engineering overhead. Stacking complex digital logic beneath high-density memory stacks introduces packaging yield risks that suppliers must still prove at sustained mass-production scale.

Sources

• SemiAnalysis post on Rubin die allocation modeling: https://x.com/SemiAnalysis_/status/2105771525605351710
• SemiAnalysis report on ECTC 2026 and Custom HBM: https://newsletter.semianalysis.com/p/ectc2026
• SemiAnalysis technical thread on NVHBM and Feynman: https://x.com/SemiAnalysis_/status/2106217837643575607
• Chiplog analysis on HBM bandwidth roadmap: https://www.chiplog.io/p/hbms-bandwidth-roadmap-and-who-is